This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.

This paper presents a technique for reducing spurious output of balanced modulators used in transmitters and arbitrary waveform generators. Two-step upconversion is a convenient way to produce a desired single-sideband (SSB) radio-frequency (RF) signal--baseband quadrature I and Q signals (which are analog outputs of direct digital frequency synthesizers) are upconverted by mixers and local oscillators (LOs)--but mismatches between the DACs in I and Q paths cause spurious output. We propose a method of dynamically matching the I and Q paths by multiplexing two DACs between I and Q paths in a pseudo-random manner. MATLAB simulation shows that multiplexing the two DACs spreads the spurious output, caused by mismatches between the two DACs, in the frequency domain, and reduces the peak level of spurious signals.

This paper describes a simple-yet-effective control method for a DC-DC buck converter with voltage mode control (VMC), with a triangular wave generator (TWG) which regulates the slope of triangular wave based on the input and output voltages of the converter. Using the proposed TWG, both the load and line transient responses are improved. Since the TWG provides a line feed-forward control for the line transient response, it increases the open-loop bandwidth, and then better dynamic performance is obtained. Additional required circuit components are only a voltage controlled linear resistor (VCR) and a voltage controlled current source (VCCS). Compared with the conventional voltage control, the proposed method significantly improves the line and load transient responses. Furthermore this triangular wave slope regulation scheme is simple compared to digital feed-forward control scheme that requires non-linear calculation. Simulation results shows the effectiveness of the proposed method.

One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique for automatic test equipment applications. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.

This paper describes the formula for dynamic power dissipation of a track/hold circuit as a function of the input frequency, the input amplitude, the sampling frequency, the track/hold duty cycle, the power supply voltage and the hold capacitance for a sinusoidal input.

This paper proposes spread-spectrum clock modulation algorithms for EMI reduction in digitally-controlled DC-DC converters. In switching regulators using PWM, switching noise and harmonic noise concentrated in a narrow spectrum around the switching frequency can cause severe EMI. Spread-spectrum clock modulation can be used to minimize EMI. In conventional switching regulators using analog control it is very difficult to realize complex spread-spectrum clocking, however this paper shows that it is relatively easy to implement spread-spectrum EMI-reduction using digital control. The proposed algorithm was verified using a power converter simulator (SCAT).

A time-interleaved ADC system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. Mismatches among channel ADCs degrade SNR and SFDR of the ADC system as a whole, and the effects of offset, gain and bandwidth mismatches as well as timing skew of the clocks distributed to the channels have been well investigated. This paper investigates the channel linearity mismatch effects in the time-interleaved ADC system, which are very important in practice but had not been investigated previously. We consider two cases: differential nonlinearity mismatch and integral nonlinearity mismatch cases. Our numerical simulation shows distinct features of such mismatch especially in frequency domain. The derived results can be useful for deriving calibration algorithms to compensate for the channel mismatch effects.

This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.

This letter presents an analysis of characteristics of multiphase buck converters with coupled inductors. We derive equivalent inductances that provide both low per-phase steady-state ripple current and fast transient response. The characteristics of coupled-inductor circuits--low per-phase ripple current and fast response--were examined and verified by circuit simulation and experiments.

This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

This paper proposes a noise reduction technology for a specific frequency band that uses the pulse coding controlled method to automatically set the notch frequency in DC-DC switching converters of communication equipment. For reducing the power levels at the frequency and its harmonics in the switching converter, we often use a frequency-modulated clock. This paper investigates a technology that prevents modulated clock frequency noise from spreading into protected frequency bands; this proposed noise reduction technology does not distribute the switching noise into some specified frequency bands. The notch in the spectrum of the switching pulses is created by the Pulse Width Coding (PWC) method. In communication devices, the noise in the receiving signal band must be as small as possible. The notch frequency is automatically set to the frequency of the received signal by adjusting the clock frequency using the equation Fn = (P+0.5)Fck. Here Fn is the notch frequency, Fck is the clock frequency, and P is a positive integer that determines the noise spectrum location. Therefore, simply be setting the notch frequency to the received signal frequency can suppress the noise present. We confirm with simulations that the proposed technique is effective for noise reduction and notch generation. Also we implement a method of automatic switching between two receiving channels. The conversion voltage ratio in the pulse width coding method switching converter is analyzed and full automatic notch frequency generation is realized. Experiments on a prototype circuit confirm notch frequency generation.

Complex bandpass ΔΣAD modulators can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. They process just input I and Q signals, not image signals, and AD conversion can be realized with low power dissipation, so that they are desirable for such low-IF receiver applications. This paper proposes a new architecture for complex bandpass Δ ΣAD modulators with cross-noise-coupled topology, which effectively raises the order of the complex modulator and achieves higher SQNDR (Signal to Quantization Noise and Distortion Ratio) with low power dissipation. By providing the cross-coupled quantization noise injection to internal I and Q paths, noise coupling between two quantizers can be realized in complex form, which enhances the order of noise shaping in complex domain, and provides a higher-order NTF using a lower-order loop filter in the complex ΔΣAD modulator. Proposed higher-order modulator can be realized just by adding some passive capacitors and switches, the additional integrator circuit composed of an operational amplifier is not necessary, and the performance of the complex modulator can be effectively raised without more power dissipation. We have performed simulation with MATLAB to verify the effectiveness of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of higher-order enhancement, and improve SQNDR of the complex bandpass ΔΣAD modulator.

In this paper, an algorithm based on Taylor series expansion is proposed to calculate the logarithm (log2x) of IEEE754 binary32 accuracy floating-point number by a multi-domain partitioning method. The general mantissa (1≤x<2) is multiplied by 2, 4, 8, … (or equivalently left-shifted by 1, 2, 3, … bits), the regions of (2≤x<4), (4≤x<8), (8≤x<16),… are considered, and Taylor-series expansion is applied. In those regions, the slope of f(x)=log2 x with respect to x is gentle compared to the region of (1≤x<2), which reduces the required number of terms. We also consider the trade-offs among the numbers of additions, subtractions, and multiplications and Look-Up Table (LUT) size in hardware to select the best algorithm for the engineer's design and build the best hardware device.

This paper describes algorithms for generating low intermodulation-distortion (IMD) two-tone sinewaves, for such as communication application ADC testing, using an arbitrary waveform generator (AWG) or a multi-bit ΣΔ DAC inside an SoC. The nonlinearity of the DAC generates distortion components, and we propose here eight methods to precompensate for the IMD using DSP algorithms and produce low-IMD two-tone signals. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of our approach.

There are two dynamics issues in vision chips: (i) The temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. These issues are discussed in [1]-[3] for the resistor network with only associated parasitic capacitances. However, in this paper we consider also parasitic inductances as well as parasitic capacitances for a more precise network dynamics model. We show that in some cases the temporal stability condition for the network with parasitic inductances and capacitances is equivalent to that for the network with only parasitic capacitances, but in general they are not equivalent. We also show that the spatial stability conditions are equivalent in both cases.

This paper presents a technique for improving the SNR and resolution of complex bandpass ΔΣADCs which are used for wireless communication systems such as cellular phone, wireless LAN and Bluetooth. Oversampling and noise-shaping are used to achieve high accuracy of a ΔΣAD modulator. However when a multi-bit internal DAC is used inside a modulator, nonlinearities of the DAC are not noise-shaped and the SNR of the ΔΣADC degrades. For the conversion of complex intermediate frequency (IF) input signals, a complex bandpass ΔΣAD modulator can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. This paper proposes a new noise-shaping algorithm--implemented by adding simple digital circuitry--to reduce the effects of nonlinearities in multi-bit DACs of complex bandpass ΔΣAD modulators. We have performed simulation with MATLAB to verify the effectiveness of the algorithm, and the results show that the proposed algorithm can improve the SNR of a complex bandpass ΔΣADC with nonlinear internal multi-bit DACs.

We have developed a high-efficiency charge-pump power supply circuit with large output current capability for mobile equipment. However, during the commercialization phase, we found that the large inrush current of 270 mA at charge-pump circuit startup-time could cause problems. In this paper we analyze the mechanism that causes this inrush current, and we propose circuitry to reduce it. We show SPICE simulation and measurement results for our proposed circuitry that confirm its effectiveness. By incorporating this circuitry, startup-time inrush current was reduced to 30 mA.

This paper presents a 0.5Vdd-step pumping method for Dickson-type charge-pump circuits that achieve high overall efficiency, including regulator circuitry, even at large output currents, and these circuits are targeted at mobile equipment applications. We have designed positive and negative charge-pump circuits which use a 0.5Vdd-step pumping method, are implemented with advanced control functions, and are fabricated with our custom CMOS process. Measured results showed that efficiency of a 2.5-stage positive charge-pump circuit before regulation is more than 93% (power supply Vdd=5 V, output voltage Vout=16.9 V 3.5Vdd, output current Iout=4 mA), and that of a 1.5-stage negative charge-pump circuit is 93% (power supply Vdd=5 V, output voltage Vout=-7.2 V -1.5Vdd, output current Iout=4 mA).

This paper describes a simple, inexpensive technique for intentionally broadening and flattening the spectrum of a DC-DC converter (switching regulator) to reduce Electro-Magnetic Interference (EMI). This noise spectrum broadening technique involves intentionally introducing pseudo-random dithering of control clock timing, which can be achieved by adding simple digital circuitry. This technique can significantly reduce noise power spectrum peaks at the DC-DC converter output. For our test case circuit, measurements showed that noise power was reduced by 5.7 dBm at the main peak, by 15.6 dBm at the second peak and by 12.8 dBm at the third peak. This simple, inexpensive technique can be applied to most conventional switching regulators by adding simple digital circuitry, and without any modification of the design of other parts.